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• 1 2021-09-14T15:45:06+00:00 Dr. Peiyi Zhao 7 Engineering plain 2021-09-17T23:31:36+00:00
  
  
  
  Email: zhao@chapman.edu
  
  College: Fowler School of Engineering
  
  
  
  
  
  Overview of scholarly research/creative activity:  Dr. Peiyi Zhao's research is focused on the development of integrated circuits to achieve ultra-low-voltage, low power, low energy consumption in order to reduce the energy consumption of IoT devices and AI processors.
  These projects will allow students to learn about clocking integrated circuits to be used in digital processors.  
  
  Specific projects working on:  Ultra-low-voltage, low power sequential element (Flip-flop, latch) for IoT
  Many IoT devices are deployed in hard-to-reach locations with little access to external power sources. IoT enabled implant devices must rely on internal batteries for a long, long extended period. Therefore, the integrated circuits of IoT devices all have strict requirement on energy; and low power has become one of top design priorities. In a processor, clock system dissipates 50%-60% of the overall power [Hsu2020]. Since clock power is one of the most significant power contributors, this project will focus on minimizing clock power by co-optimizing clock tree and flip-flop (FF).    
      
  This project addresses power consumption of clock system in the following ways: (1) Co-optimizing clock tree and FF simultaneously by using dual-clocking-gating instead of only using traditional toggle-based clock gating. In the dual-clocking-gating method, clock gating is employed both in clock tree and inside flip-flop. (2) Employing new clock gating control structure to reduce its area and power overhead. (3) In FF, clock gating will be used. In addition, the clock number will be reduced. 
  [Hsu2020 Intel] S.Hsu, et al. “Low-Clock-Power Digital Standard Cell IPs for High-Performance," 2020 IEEE Symposium on VLSI Circuits, pp.100-101.
  
  Number of students looking to work with: 1-2
  
  Time commitment for students:  Meet once per week, expect 3 hours commitment to project/week.
  
  Requirements for students who work with you:  Complete CPSC 330 Digital Logic or EENG300 Electronics and Circuits.
  
  When students are needed: Fall 2021 and Spring 2022
  
  What would students be expected to do​​​​​​: Design digital integrated circuits using tools from Cadence, Synosys, Mentor Graphics; Measure power and speed of integrated circuits.