Dr. Peiyi Zhao
Email: zhao@chapman.edu
College: Fowler School of Engineering
Department: Computer Engineering
Overview of scholarly research/creative activity: Dr. Peiyi Zhao is an Associate Professor in Fowler School of Engineering. His main research area is ENERGY EFFICIENT digital integrated circuit, specially clocking storage element, flip-flop. Other areas include ultra low power circuit working at near threshold voltage for medical device, novel device with super low standby energy.
Specific projects working on: Data centers will consume 8% of the electricity worldwide by 2030. In data centers(DC) , processors are the source of power consumption. In processors, one of the two dominant power consumption contributors are flip-flops [FFs] which account for about 20% of the dynamic power of processors. This is because there are millions of flip flops each switches one billion times per second in a processor. Further each flip-flop uses multiple clocked transistors that are always switching even when the input does not change, hence they are constantly consuming power. Due to Energy Cascade Effect in data centers, 1 Watt saved at the processor saves approximately 2.84 Watts of total consumption in DC. Reducing power consumption in FFs will reduce power consumption in DC. We will design a low power flip flop using clock gating technique. Using laundry machine as an analogy, when there is no clothes in the laundry machine, it does not need to rotate. That is exactly what the clock gating will do to the clocked transistors in a processor: when input data does not change, the clocked transistors do not need to constantly switch, therefore, clock gating can reduce power consumption. Tools used in this project are as follows: **Virtuoso tool from Cadence: for design schematic and layout. **Calibre tool from Mentor Graphic: for Design rule check, schematic vs. layout check, parameter extraction. **Hspice from Synopsys: for simulation to obtain data of power consumption and speed
Number of students looking to work with: 1-2
Time commitment for students: Meet weekly, expected 5 hours commitment to project / week
Requirements for students who work with you: Have completed CPSC330 Digital Logic, have knowledge of CMOS transistor
When students are needed: Fall 2020, Interterm 2021, Spring 2021, Summer 2021
What would students be expected to do: lab experiments using Virtuoso schematic/layout tools set, literature summary