Dr. Peiyi Zhao
Email: zhao@chapman.edu
Website: www1.chapman.edu/~zhao
College: Fowler School of Engineering
Overview of scholarly research/creative activity:
Dr. Zhao’s research interests include the design of low power/energy integrated circuits for processors in laptop/or in servers in data center using CMOS transistors, for example, low power clocking systems in processors.
His research also includes Approximate-computing heterogeneous Register File for Machine learning accelerator.
Specific projects working on:
Computing power consumed by AI processors has doubled every 3.4 months. The largest AI processor in 2021, Cerebras CS-2 processor, used more than 2 trillion transistors and drew up to 23KW of power aiming for training machine-learning neural networks [Cerebras2021]. The number of computations in neural networks has skyrocketed, resulting in a prohibitively significant increase in power consumption, making machine learning (ML) one of the most energy-expensive workloads for computing[Sanyal2022, Liu2022]. Machine learning will soon face a slowdown due to it’s alarmingly ever-increasing power consumption [Lohn2022].
Approximate computing (AC) is an efficient power-reduction technique which trades quality with power for error-resilient AI applications. One of the key challenges for AC in machine learning refers to the design and optimization of approximate computing ML accelerators(MLA)[Henke2022].
Machine learning accelerators(MLA) are made of a large array of Processing Elements(PE).
PEs consist of Register File (RegFIle) which is built from array of flip-flops (FFs) and other logic gates, and contributes a significant amount of power (39% and area (35%) within the PEs and limit the overall chip level performance, power[Hsu2022 Intel].
Existing RegFiles have limitations and overheads of power, delay, and area. To address these challenges, this project aims to establish a RegFile consisting of inaccurate FFs and accurate FFs in a heterogeneous way.
Number of students looking to work with:
1-2
When students are needed:
Interterm 2024
Spring 2024
What students need to work with Dr. Zhao:
*Take CPSC 366 digital logic II (required for CE,EE, CE minor), or take CPSC 465 Integrated circuits, or take CPSC 298 Integrated circuits (with CPSC330).
What students would be doing:
Experiment to design circuit, simulate them, measure power and delay using Cadence /Synopsys/Mentor Graphic tools
Time commitment for students:
Meet once/week, expected 3 hrs commitment to project/week
